1. Field of the Invention
The present invention relates to a data memory apparatus including at least one memory device forming a memory map which includes a plurality of memory areas.
2. Description of the Related Art
FIG. 11 shows a structure of a conventional data memory apparatus 300. The data memory apparatus 300 includes memory devices 102, 104, 106, 108, 110, 112, 114 and 116 and a controller 140 for controlling the memory devices 102, 104, 106, 108, 110, 112, 114 and 116. The memory devices 102, 104, 106, 108, 110, 112, 114 and 116 and the controller 140 are connected to one another through a conductive line 120. Data is read from or written to the memory devices 102, 104, 106, 108, 110, 112, 114 and 116 by access from the controller 140.
The controller 140 in the data memory apparatus 300 is connected to a processor 130.
The data memory apparatus 300 having such a structure is in wide use for computers and consumer electronic appliances. The data memory apparatus 300 stores various data such as programs so that the processor 130 can execute any specified software.
FIG. 12 shows a structure of a memory map in the data memory apparatus 300. The memory map has a memory area of 9 megabytes (8 megabyte RAM area+1 megabyte VIDEO/ROM area). The VIDEO/ROM area is a memory area for VIDEO RAM and system ROM. The memory devices 102, 104, 106, 108, 110, 112, 114 and 116 are each assigned to a one-megabyte RAM area.
Recently, higher-speed and more complicated processing has been demanded by users. In order to comply with these demands, a large volume of data need be read from and written into the memory devices 102, 104, 106, 108, 110, 112, 114 and 116. Therefore, the data transfer speed required between the controller 140 (FIG. 11) and the memory devices 102, 104, 106, 108, 110, 112, 114 and 116 has been increased remarkably.
However, the controller 140 and the memory devices 102, 104, 106, 108, 110, 112, 114 and 116 are usually connected to each other on a PC substrate or a silicon substrate through conductive line 120 formed of copper or aluminum. When the signal frequency is increased to raise the data transfer speed, the signal is disrupted by reflections or the like generated at input ends of the controller 140 and the memory devices 102, 104, 106, 108, 110, 112, 114 and 116. In order to avoid such disturbance of the signal, conductive line 120 needs to be shortened as the signal frequency is increased.
When conductive line 120 is shortened, the number of memory devices which can be connected to conductive line 120 is reduced. As a result, memory capacity is reduced. This is contrary to the current demand for processing a large volume of data.
Among various types of processing demanded by the users, some types, such as image processing, are complicated and require frequent memory access; and some types, such as wordprocessing, are relatively simple and require less frequent memory access. However, conventionally, different types of data (including programs) which are accessed at significantly different frequencies (i.e., the number of times a type of data is accessed) are mapped uniformly in each area of the memory map. The structure shown in FIG. 12 is of such a conventional memory map which is flat in terms of speed.
One conventional method for increasing the memory access speed utilizes a cache memory 150 (FIG. 11), which is provided in the processor 130. By this method, however, a part of the data in the memory map, which is flat in terms of speed, is merely copied into the cache memory 150. When a cache hit miss occurs, the memory devices 102, 104, 106, 108, 110, 112, 114 and 116, which are equal in terms of speed, are accessed.